High speed trench DMOS

ABSTRACT

A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.

FIELD OF THE INVENTION

[0001] The present invention relates generally to MOSFET transistors andmore generally to DMOS transistors having a trench structure.

BACKGROUND OF THE INVENTION

[0002] DMOS (Double diffused MOS) transistors are a type of MOSFET(Metal On Semiconductor Field Effect Transistor) that use diffusion toform the transistor regions. DMOS transistors are typically employed aspower transistors to provide high voltage circuits for power integratedcircuit applications. DMOS transistors provide higher current per unitarea when low forward voltage drops are required.

[0003] A typical discrete DMOS circuit includes two or more individualDMOS transistor cells which are fabricated in parallel. The individualDMOS transistor cells share a common drain contact (the substrate),while their sources are all shorted together with metal and their gatesare shorted together by polysilicon. Thus, even though the discrete DMOScircuit is constructed from a matrix of smaller transistors it behavesas if it were a single large transistor. For a discrete DMOS circuit itis desirable to maximize the conductivity per unit area when thetransistor matrix is turned on by the gate.

[0004] One particular type of DMOS transistor is a so-called trench DMOStransistor in which the channel is formed vertically and the gate isformed in a trench extending between the source and drain. The trench,which is lined with a thin oxide layer and filled with polysilicon,allows less constricted current flow and thereby provides lower valuesof specific on-resistance. Examples of trench DMOS transistors aredisclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931.

[0005] One problem frequently experienced with trench DMOS transistorsis known as punch-through. Punch-through, which arises when thetransistor channel is depleted, typically takes the form of anon-destructive leakage current prior to avalanche breakdown. It hasbeen found that punch-through is particularly deleterious at highertransistor cell densities, notably at densities greater than about18M/in³. While punch-through can have many causes, one significant causeof punch-through occurs during the formation of the trench gate. Inparticular, after the trench has been etched, a sacrificial oxidationstep is performed to smooth the trench sidewalls, which is then followedby deposition of the thin oxide layer. During the sacrificial oxidationand oxide deposition steps, dopant material leaches out of the adjacentchannel (the so-called p-body) because dopant material (typically boron)segregates from the silicon into the oxide during the sacrificialoxidation step, which is performed at high temperatures. This problem isexacerbated at higher cell densities, because the relative width of thechannel decreases with respect to the surface area encompassed by thetrench.

[0006] Punch-through is also aggravated when polysilicon is deposited tofill the trench because the dopant (typically phosphorous) employed inthe polysilicon can penetrate through the gate into the p-body, whicheffectively reduces the concentration of carriers in the channel. Thisproblem becomes more severe as the thickness of the gate oxide layerlining the trench is reduced.

[0007] U.S. Pat. No. 5,072,266 discloses a conventional sequence ofprocessing steps that are employed to fabricate a trench DMOStransistor. In this process, the p-body channel and the source regionsare formed before the trench. As previously mentioned, however, duringthe formation of the trench, dopant materials can leach out of thep-body, increasing punch-through. As a result, the depth of the trenchand the p-body must be increased to compensate for the increase inpunch-through. Moreover, the source regions may also be adverselyeffected during the formation of the trench because of silicon defectsproduced in the source regions during the oxidation steps used informing the trench gate.

[0008] U.S. Pat. No. 5,468,982 attempts to reduce punch-through byforming the p-body after the trench gate has been etched and filled.This approach is not entirely satisfactory, however, since the formationof the p-body requires a diffusion step that involves high temperatures(typically 1100-1150° C.). These high temperatures allow the dopantmaterial in the polysilicon that fills the trench to penetrate throughthe gate oxide at a greater rate, thus contributing to an increase inpunch-through.

[0009] Another problem with existing trench DMOS is switching speed.There is a significant emphasis in the industry toward producingdiscrete DMOS circuits with higher cell densities. However, as celldensity is increased, trench widths must be shrunk in order to achievedesign requirements, and the narrower trench widths result in highergate resistance. Consequently, switching speed becomes an importantconsideration.

[0010] Polycide, such as WSi₂ and TiSi₂, and refractory metals andalloys such as W and TiW, have been used in advanced logic processes toincrease the switching speeds of devices and IC circuits. However, it isstill not common to use polycide or refractory metal techniques intrench DMOS, due in part to the fact that the higher switching speedswhich are theoretically achievable with these materials has not beenrealized. The reason for this can be understood by considering a typicalprior art trench DMOS equipped with a double-layer gate. The gate isproduced by selective CVD tungsten. In trench DMOS of this type, theP-body and source are formed before the trench gate is formed.Transistors of this type have at least two drawbacks. Firstly, silicondefects are easily formed in the source region during subsequentoxidation processes, such as sacrificial and gate oxidations. Since thesource region is typically heavily doped with arsenic, this results inpoor gate oxide integrity in this region. Secondly, transistors of thistype typically have a deeper source junction depth due to the subsequentoxidation processes, which requires a deeper P-body and trench in orderto prevent punch-through. Consequently, the device has higher parasiticcapacitance, which reduces the benefit gained from the tungsten/polygate.

[0011] There thus remains a need in the art for a trench DMOS, and amethod for making the same, in which the trench DMOS has a low gateresistance and low capacitance, thereby reducing the distributed RC gatepropagation delay and improving switching speed for high frequencyapplications. There is also a need in the art for a method for making atrench DMOS that reduces or eliminates punch-through. These and otherneeds are met by the present invention, as hereinafter disclosed.

SUMMARY OF THE INVENTION

[0012] The present invention relates to methods for creating trenchDMOS, and to the trench DMOS so made. In accordance with the invention,polycide and refractory techniques are used to make trench DMOS whichexhibit low gate resistance, low gate capacitance, reduced distributedRC gate propagation delay, reduced punch-through, and improved switchingspeeds for high frequency applications.

[0013] In one aspect, the present invention relates to a method formaking trench DMOS, and to the trench DMOS so made. In accordance withthe method, the source, which may be an n+ source, is formed after gateoxidation. This allows the junction depth to be controlled within a veryshallow range (e.g., 0.2 to 0.5 μm), which reduces parasitic capacitanceby allowing the use of a shallower P-body and shallower trench depthwithout increasing the risk of drain/source punch-through. The formationof the source after gate oxidation is also advantageous in that itprovides for improved gate oxide integrity, since it eliminates silicondefects in the source region (which is typically heavily doped witharsenic) that would otherwise result from the oxidation processes.Moreover, this methodology results in less stress or void formationbetween the polysilicon and polycide or refractory metal, since thedevice is not exposed to any high temperature processes after CVDpolycide or refractory metal deposition.

[0014] In another aspect, the present invention relates to a trench DMOShaving a gate construction having at least three layers, and to a methodfor making such a trench DMOS. In the gate construction, the firstlayer, which is typically disposed on the gate oxide layer, comprisesundoped polysilicon, while the second layer comprises doped polysiliconand the third layer comprises a material selected from the groupconsisting of polycides and refractory metals. The first layer serves asa buffer to block phosphorous penetration through the gate oxide duringBPSG flow, thereby preventing drain/source punch-through.

[0015] In still another aspect, the present invention relates to amethod for making a trench DMOS, and to trench DMOS so made, in whichthe dopant material is prevented from leaching out of the P-body duringtrench formation. In accordance with the method, trench formation isaccomplished by the use of a patterned trench mask in conjunction withan etching process. Before the mask is removed, the side walls of thetrench may be smoothed with a sacrificial oxide layer. Since trenchformation is completed prior to removal of the mask, and since the maskserves as a cap or barrier to the dopant material, leaching of thedopant material from the P-body is substantially eliminated, andpunch-through is consequently reduced.

[0016] In yet another aspect, the present invention relates to a trenchDMOS, and a method for making the same, in which a portion of the gatelayer is disposed above the source area so that it is further from thedrain than the source area. The resulting structure has a lower gateresistance, especially in a shallow trench device, and higher switchingspeeds.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 shows a schematic cross-sectional view of one embodiment ofa trench DMOS transistor constructed in accordance with the presentinvention;

[0018] FIGS. 2A-2G are schematic cross-sectional views illustrating asequence of processing steps for forming a DMOS transistor in accordancewith the present invention;

[0019] FIGS. 3A-3B are schematic cross-sectional views illustrating asequence of processing steps for forming a DMOS transistor in accordancewith the present invention; and

[0020] FIGS. 4A-4B are schematic cross-sectional views illustrating asequence of process steps for forming a DMOS transistor in accordancewith the present invention.

DETAILED DESCRIPTION

[0021] The present invention provides methods for creating trench DMOSwhich utilize polycide and refractory techniques. The trench DMOS madein accordance with these methods exhibit low gate resistance, low gatecapacitance, reduced distributed RC gate propagation delay, reducedpunch-through, and improved switching speeds for high frequencyapplications.

[0022]FIG. 1 illustrates a trench DMOS structure 1 which is made inaccordance with the present invention. The structure includes an n+substrate 3 on which is grown a lightly n-doped epitaxial layer 5.Within the doped epitaxial layer, a body region 7 of oppositeconductivity is provided. A doped epitaxial layer 9 that overlies mostof the body region serves as the source. A hexagonally shaped trench 11is provided in the epitaxial layer, which is open at the upper surfaceof the structure. The trench associated with each transistor celldefines a cell region 13 that is also hexagonally shaped in horizontalcross-section. Within the cell region, the body region rises to theupper surface of the structure and forms an exposed pattern 15 in ahorizontal cross section at the top surface of the cell region.

[0023] The MOSFET shown in FIG. 1 has its gate positioned in avertically oriented rectangular trench. This structure is often called atrench vertical DMOSFET. It is “vertical” because the drain contactappears on the back or underside of the substrate and because thechannel flow of current from source to drain is approximately vertical.This set-up minimizes the higher resistance associated with bent orcurved current paths or with parasitic field effect constructions. Thedevice is also doubly diffused (denoted by the prefix “D”) because thesource region is diffused into the epitaxial material on top of aportion of the earlier-diffused body region of opposite conductivitytype. This structure uses the trench side wall area for current controlby the gate and has a substantially vertical current flow associatedwith it. As previously mentioned, this device is particularlyappropriate for use as a power switching transistor where the currentcarried through a given transverse silicon area is to be maximized.

[0024] It should be noted that the transistor cell 13 need not have ahexagonal shape for basic transistor operation, but more generally mayhave any polygonal shape. However, a regular rectangular shape and aregular hexagonal shape are the most convenient for layout purposes.Alternatively, rather than having a closed cell geometry as depicted inthe figures, the transistor cell may have an open or stripe geometry.Examples of various transistor cell geometries are shown in thepreviously mentioned, references. Moreover, it should also be noted thatin FIG. 1 and the figures that follow, only the substrate, itsassociated doped regions and the trench are shown. Other layers such asoverlying insulating layers, gate structures and conductiveinterconnects are not shown for the sake of clarity and are well knownto those of ordinary skill in the art.

[0025] FIGS. 2A-2G shows a first embodiment of the method of the presentinvention that may be used to form a DMOS device of the type depicted inFIG. 1. In FIG. 2A, an N-doped epitaxial layer 21 is grown on aconventionally N+ doped substrate 23. The epitaxial layer is typically5.5 microns in thickness for a 30 V device. Next, P-body region 25 isformed in an implantation and diffusion step. Since the P-body implantis uniform across the substrate, no mask is needed. The P-body regionsare boron implanted at 40 to 60 KEV with a dosage of 5.5×10¹³/cm³.

[0026] In FIG. 2B, a mask oxide layer is formed by covering the surfaceof the epitaxial layer with an oxide layer, which is then conventionallyexposed and patterned to leave mask portions 27. Mask portions 27 areused for defining the location of the trenches 29, which are dry etchedthrough the mask openings by reactive ion etching to a depth thattypically ranges from 1.5 to 2.5 microns.

[0027] In FIG. 2C, the mask portions are removed, typically by a bufferoxide etch or an HF etch. Since the steps of trench formation arecompleted prior to removal of the patterned trench mask, and since thepatterned trench mask serves as a cap or buffer during the trenchforming process, dopant material does not leach out of the P-body. Thisis in contrast to previously mentioned U.S. Pat. No. 5,072,266, in whichthe trench mask is removed before performing the sacrificial oxide step,thus allowing dopant material to leach out of the p-body. By preventingdopant material from leaching out of the P-body, the methodology of thepresent invention reduces punch-through.

[0028] After removal of the mask portions, a gate oxide layer 31 isdeposited on the entire structure so that it covers the trench walls andthe surface of p-body 25. Gate oxide layer 31 typically has a thicknessin the range of 500-800 angstroms.

[0029] In FIG. 2D, after deposition of the gate oxide layer, a layer ofundoped polysilicon 35 is deposited, followed by a layer of dopedpolysilicon 37, i.e., polycrystalline silicon doped with phosphorouschloride or implanted with arsenic or phosphorous to reduce itsresistivity, which resistivity is typically within the range of 20 ohm.The undoped polysilicon layer acts as a buffer layer to blockphosphorous penetration through the gate oxide layer during BPSG flow,thereby preventing drain/source punch-through. Next, a layer of polycide39 such as WSi₂ or TiSi₂ or a layer of a refractory metal such as TiW orW is deposited.

[0030] In FIG. 2E, the undoped poly, doped poly, and polycide layers areetched to expose the portion of the gate oxide layer that extends overthe surface of the P-body. Next, a photoresist masking process is usedto form a patterned masking layer 41. The patterned masking layerdefines the N-source regions 43, which are subsequently formed by animplantation and diffusion process using arsenic or phosphorous. Forexample, the first source regions may be implanted with arsenic at 80KEV to a concentration that is typically within the range of 8×10¹⁵ to1.2×10¹⁶/cm³. After implantation, the arsenic is diffused to a depth ofapproximately 0.5 microns. After formation of the N-source regions, themasking layer is removed in a conventional manner to form the structuredepicted in FIG. 2F, and one or more P-source regions 45 are implanted.

[0031] The trench DMOS transistor is completed by forming and patterninga BPSG layer over the structure to define BPSG regions associated withthe gate electrodes. The BPSG are patterned through a contact mask andetching process, after which successive layers of Ti/TiN 48 and AL/Si/Cu50 are deposited through a metal mask and etching process. Also, a draincontact layer is formed on the bottom surface of the substrate. Finally,a pad mask is used to define pad contacts.

[0032] FIGS. 3A-3B illustrate a second embodiment of the method of thepresent invention. In this embodiment, a trench DMOS is formedsubstantially in accordance with the steps illustrated in FIGS. 2A-2D.However, after the deposition of the layer of polycide or refractorymetal 51 over the layers of undoped polysilicon 53, doped polysilicon55, and gate oxide 56, a polysilicon mask 57 is placed over the trench59, and the resulting structure is subjected to etching to remove theunmasked polysilicon and polycide layers. The trench DMOS transistor isthen completed in a manner similar to that depicted in FIGS. 2E-2G toyield the device depicted in FIG. 3B. In the finished device, a portion61 of the gate layer is disposed above the source area 63, so that thedistance between the drain and the portion 61 of the gate layer isgreater than the distance between the drain and the source. As a result,the configuration has a lower gate resistance, especially in a shallowtrench device, thereby achieving higher switching speeds.

[0033] FIGS. 4A-4B illustrate a third embodiment of the method of thepresent invention. In this embodiment, the trench DMOS is formed in amanner similar to that used to form the devices depicted in FIGS. 3A-3B,except that the layer of doped polysilicon 65 employed is sufficientlythick to fill the trench 67. As in the device depicted in FIGS. 3A-3B,at least a portion 69 of the gate layer in the finished device isdisposed above the source area 71 so that the distance between the drainand at least a portion of the gate layer is greater than the distancebetween the drain and the source. This configuration, like theconfiguration depicted in FIGS. 3A-3B, also has a lower gate resistance,especially in a shallow trench device, and higher switching speeds.

[0034] In accordance with the methodology of the present invention, theN-source region is formed after gate oxidation so that the junctiondepth can be controlled to very shallow depths (e.g., within the rangeof 0.2 to 0.5 μm), depending on the BPSG flow temperature cycle whichwill typically range from 900 to 950° C. The parasitic capacitance isthus reduced, because shallower P-body and trench depths are achievablewithout having drain/source punch-through. Moreover, less stress or voidformation results between the polysilicon and polycide or refractorymetal, since no high temperature process is performed after CVD polycideor refractory metal deposition.

[0035] In the various embodiments of the present invention,punch-through may also be reduced by filling the trench with polysiliconin a two step process. In the first step, a layer of undoped polysiliconis deposited over the gate oxide layer to line the sidewalls of thetrenches. The undoped polysilicon layer is followed by the deposition ofa layer of doped polysilicon. Typically, the thickness of the dopedpolysilicon layer is greater than the thickness of the undopedpolysilicon layer. For example, the ratio of the thickness of the dopedpolysilicon layer to the undoped polysilicon layer may be 7:1 orgreater, with a typical total thickness of about 8,000 A.

[0036] The undoped polysilicon layer may be advantageously employed as abuffer layer to inhibit the penetration of dopant material through thegate oxide layer and into the P-body, thus further reducingpunch-through. This two step process may be used when the trench isformed prior to the removal of the trench mask. Alternatively, the twolayer deposition process may be used by itself to reduce punch through.That is, the trench may be filled with undoped and doped layers ofpolysilicon even when the trench mask is removed before the formation ofthe trench.

[0037] Although various embodiments are specifically illustrated anddescribed herein, it will be appreciated that modifications andvariations of the present Invention are covered by the above teachingsand are within the purview of the appended claims without departing fromthe spirit and intended scope of the invention. For example, the methodof the present invention may be used to form a trench DMOS in which theconductivities of the various semiconductor regions are reversed fromthose described herein.

What is claimed is:
 1. A method for forming a trench DMOS, comprisingthe steps of: providing an article comprising a substrate of a firstconductivity type and a body region of a second conductivity type, saidarticle having a trench which extends through said body region and saidsubstrate; depositing a gate oxide layer in the trench; forming a gatein the trench, said gate having at least one layer comprising a materialselected from the group consisting of polycide and refractory metals;and forming a source region in the body region; wherein the sourceregion is formed after the gate oxide layer is deposited.
 2. The methodof claim 1 , wherein said gate comprises a first layer comprisingundoped polysilicon, a second layer comprising doped polysilicon, and athird layer comprising a material selected from the group consisting ofpolycide and refractory metals.
 3. The method of claim 2 , wherein saidfirst layer is adjacent to said gate oxide layer.
 4. The method of claim1 , wherein said gate has at least one layer comprising a refractorymetal.
 5. The method of claim 4 , wherein said refractory metal isselected from the group consisting of W and TiW.
 6. The method of claim1 , wherein said gate has at least one layer comprising polycide.
 7. Themethod of claim 6 , wherein said polycide is selected from the groupconsisting of WSi₂ and TiSi₂.
 8. The method of claim 1 , wherein saidtrench is formed by providing a masking layer defining at least onetrench, and forming the trench defined by the masking layer.
 9. Themethod of claim 8 , wherein said masking layer is disposed on said bodyregion before said trench is formed.
 10. The method of claim 8 , whereinsaid mask is removed after said trench is formed.
 11. The method ofclaim 1 , wherein said body region is a P-body.
 12. The method of claim1 , wherein said body region is formed by implanting and diffusing adopant into the substrate.
 13. The method of claim 1 , wherein the bodyregion is disposed on said substrate.
 14. The method of claim 1 ,wherein the source region is a source region of said first conductivitytype.
 15. The method of claim 14 , further comprising the step offorming a source region of a third conductivity type.
 16. The method ofclaim 15 , wherein the first conductivity type is n+ and the thirdconductivity type is p+.
 17. The method of claim 1 , wherein said sourceregion is an n+ source region.
 18. The method of claim 1 , wherein saidsource region is adjacent to said trench.
 19. The method of claim 1 ,wherein said source region is formed with a junction depth of less thanabout 0.5 μm.
 20. The method of claim 1 , wherein said source region isformed with a junction depth within the range of about 0.2 to about 0.5μm.
 21. The method of claim 1 , further comprising the step of: forminga patterned BPSG layer over said trench.
 22. The method of claim 21 ,wherein the patterned BPSG layer is formed over the trench with a flowtemperature cycle ranging from about 900 to about 950° C.
 23. A trenchDMOS made in accordance with the method of claim 19 , said trench DMOScomprising a plurality of gate electrodes, and wherein each of said gateelectrodes has a BPSG region associated with it.
 24. A trench DMOS madein accordance with the method of claim 1 .
 25. The trench DMOS of claim24 , further comprising a drain, wherein the distance between at least aportion of said gate and said drain is greater than the distance betweensaid source region and said drain.
 26. The method of claim 1 , whereinthe step of forming a gate in the trench includes the steps of fillingthe trench with polysilicon, and depositing on the polysilicon a layercomprising a material selected from the group consisting of polycide andrefractory metals.
 27. A method for making a trench DMOS, comprising thesteps of: providing a substrate of a first conductivity type; forming abody region on the substrate, said body region having a secondconductivity type; forming a masking layer defining at least one trench;forming the trench defined by the masking layer, said trench extendingthrough the body region and the substrate; forming a gate in the trench,said gate comprising a first layer comprising undoped polysilicon, asecond layer comprising doped polysilicon, and a third layer comprisinga material selected from the group consisting of polycide and refractorymetals; and forming a first source region of the first conductivity typein the body region adjacent to the trench.
 28. The method of claim 27 ,further comprising the step of: forming a second source region of athird conductivity type adjacent to said first source region.
 29. Themethod of claim 28 , wherein said first source region is an n+ source,and wherein said second source region is a p+ source.
 30. The method ofclaim 27 , wherein said trench is covered with an insulating layerbefore said gate is formed.
 31. The method of claim 30 , wherein saidinsulating layer is a gate oxide layer.
 32. A trench DMOS, comprising: asubstrate having a first conductivity type; a body region having asecond conductivity type; a trench which extends through said bodyregion and said substrate; a gate, disposed in said trench; a sourceregion disposed in said body region; and a drain; wherein the distancebetween at least a portion of said gate and said drain is greater thanthe distance between said source region and said drain.
 33. The trenchDMOS of claim 32 , wherein said substrate has a major surface which issubstantially planar, and wherein the axis is perpendicular to saidmajor surface.
 34. The trench DMOS of claim 32 , further comprising agate oxide layer disposed between said gate and the surface of saidtrench.
 35. The trench DMOS of claim 32 , wherein said gate comprises afirst layer comprising undoped polysilicon, a second layer comprisingdoped polysilicon, and a third layer comprising a material selected fromthe group consisting of polycide and refractory metals.
 36. The trenchDMOS of claim 35 , wherein said first layer is adjacent to said gateoxide layer.
 37. The trench DMOS of claim 32 , wherein said gate has atleast one layer comprising a refractory metal.
 38. The trench DMOS ofclaim 37 , wherein said refractory metal is selected from the groupconsisting of W and TiW.
 39. The trench DMOS of claim 32 , wherein saidgate has at least one layer comprising polycide.
 40. The trench DMOS ofclaim 39 , wherein said polycide is selected from the group consistingof WSi₂ and TiSi₂.
 41. The trench DMOS of claim 32 , wherein said bodyregion is a P-body.
 42. The trench DMOS of claim 32 , wherein said bodyregion is disposed on said substrate.
 43. The trench DMOS of claim 32 ,wherein the source region is a source region of said first conductivitytype.
 44. The trench DMOS of claim 32 , further comprising a sourceregion of a third conductivity type.
 45. The trench DMOS of claim 44 ,wherein the first conductivity type is n+ and the third conductivitytype is p+.
 46. The trench DMOS of claim 32 , wherein said source regionis an n+ source region.
 47. The trench DMOS of claim 32 , wherein saidsource region is adjacent to said trench.
 48. The trench DMOS of claim32 , wherein said source region has a junction depth of less than about0.5 μm.
 49. The trench DMOS of claim 32 , wherein said source region hasa junction depth within the range of about 0.2 to about 0.5 μm.
 50. Thetrench DMOS of claim 32 , further comprising a patterned BPSG layerdisposed over said trench.
 51. A method for forming a trench DMOStransistor cell, comprising the steps of: providing an articlecomprising a substrate of a first conductivity type and a body region ofa second conductivity type, said article having a trench which extendsthrough said body region and said substrate; forming a gate overlyingsaid trench and said body region, said gate having at least one layercomprising a material selected from the group consisting of polycide andrefractory metals; placing a mask over the trench; removing the unmaskedportions of the gate; and forming a first source region in the bodyregion.
 52. The method of claim 51 , wherein the trench and body regionare lined with an insulating layer prior to formation of the gate. 53.The method of claim 51 , wherein the first source region is of the firstconductivity type.
 54. The method of claim 51 , wherein the first sourceregion is adjacent to the trench.
 55. The method of claim 51 , furthercomprising the step of: forming a second source region of a thirdconductivity type.
 56. The method of claim 51 , wherein the first sourceregion is an n+ source region.
 57. The method of claim 55 , wherein thefirst source region is an n+ source region, and wherein the secondsource region is a p+ source region.
 58. The method of claim 51 ,wherein the step of forming the gate includes the steps of filling thetrench with polysilicon, and depositing on the polysilicon a layercomprising a material selected from the group consisting of polycide andrefractory metals.
 59. The trench DMOS of claim 51 wherein said gateincludes at least one layer comprising a material selected from thegroup consisting of polycide and refractory metals.